Faculty

Po-Tsang Huang

Research Direction:
Digital Integrated Circuit Design
3D Integrated Circuit Design
Memory Circuit Design
System on One Chip design
Forward-Looking Process Circuit Design Method

Education:
2004 – 2010 Institute of Electronics, National Yang Ming Chiao Tung University, Ph. D.
2002 – 2004 Institute of Electronics, National Yang Ming Chiao Tung University, Master
1997 – 2002 Institute of Electronics, National Yang Ming Chiao Tung University, Bachelor

Experience:
2022.12 – 2025.08 Associate Professor, International College of Semiconductor Technology, National Yang Ming Chiao Tung University
2017.02 – 2022.12 Assistant Professor, International College of Semiconductor Technology, National Yang Ming Chiao Tung University
2014.11 – 2016.11 Visiting Postdoctoral Scholar, Electrical Engineering Department, UCLA
2015.10 – 2017.01 Associate Research Fellow, Department of Electrical and Computer Engineering, NCTU
2014.01 – 2015.10 Assistant Research Fellow, Department of Electrical and Computer Engineering, NCTU
2011.01 – 2013.12 Assistant Research Fellow, Department of Electronics Engineering, NCTU

Research Interests：
     Our major research goal for the next decade is to explore pioneering “sustainable circuits and systems”, focusing on carbon-aware system-design-technology co-optimization, carbon-aware computing, energy-efficient design techniques and methodologies of system integration for both power-limited and energy-limited applications. Our research spans across multiple levels of design abstraction from solid-state circuits, architectures and systems.

• SoC/SiP architecture/platform for IoT, AI & communication applications

• Carbon-aware system-design-technology co-optimization
• Accelerator design for neural networks using 3D-SRAM or 3D-DRAM
• Hierarchical configurable interconnect with 3D-SRAM for memory-centric computingW
• Fault-tolerant 3D-DRAM controller
• Memory sub-system for heterogeneous multi-core SoC/SiP
• Accelerator-rich and memory-rich computer architectures for domain-specific computing
• System-level power analysis and noise reduction in HPC/3DIC
• Accelerator/reconfigurable architecture for SDR or resilient wireless network

• Circuit/technology co-design using monolithic/TSV 3DIC, emerging memory & devices

• Low-power high-density embedded memory design and diagnosis methodology (SRAM, Register-File, FIFO, CAM/TCAM)
• Computation-in-memory or in-memory searching engine for neural networks (SRAM, ReRAM, FeFET, FeRAM)
• Fault/Age-Aware Memory Design
• Energy-Efficient digital IC (VLSI) design using emerging memory & devices
• Power management and data communications for 3D-IC (M3D & TSV 3D-IC)
• Ultra-low voltage IC design for IoT and biomedical applications