演講/活動
2024-12-04 15:12:12陳秋雲【演講公告】Machine Learning for Chip Design and Design Automation for Machine Learning Chips
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Speaker：Prof. Jiang Hu ,Texas A&M U, IEEE Fellow
DATE：2024 . 12 . 12
TIME： 10:30am-12:00
LOCATION：陽明交通大學-工程四館ED417B
Sign up link： https://docs.google.com/forms/d/e/1FAIpQLScpd45oCI2M1xbfSgna7CP4KZebVm83jB7_FfU8Wx2HAmQC5w/viewform
Abstract：
Machine learning provides a promising approach to chip design predictions, which play a critical role in expediting design turnaround time. Nevertheless, the non-determinism of certain design automation software introduces variability in data labels, posing a substantial hurdle to effective ML model training. In the first part of this talk, we will delve into the utilization of CNNs for predicting design rule violations, along with a stochastic technique to mitigate the challenges stemming from noisy data labels generated by parallel routers. The growing demand for CNN computation necessitates the development of specialized CNN hardware accelerators. In the second part, the talk will be focused on the co-optimization of CNN hardware architecture and dataflow mapping—an intricate problem characterized by an extensive discrete solution space. We will introduce an innovative analytical approach, making a significant advancement over current state-of-the-art methods in improving inference speed and reducing power consumption as well as computational cost.
Speaker：Prof. Jiang Hu ,Texas A&M U, IEEE Fellow
DATE：2024 . 12 . 12
TIME： 10:30am-12:00
LOCATION：陽明交通大學-工程四館ED417B
Sign up link： https://docs.google.com/forms/d/e/1FAIpQLScpd45oCI2M1xbfSgna7CP4KZebVm83jB7_FfU8Wx2HAmQC5w/viewform
Abstract：
Machine learning provides a promising approach to chip design predictions, which play a critical role in expediting design turnaround time. Nevertheless, the non-determinism of certain design automation software introduces variability in data labels, posing a substantial hurdle to effective ML model training. In the first part of this talk, we will delve into the utilization of CNNs for predicting design rule violations, along with a stochastic technique to mitigate the challenges stemming from noisy data labels generated by parallel routers. The growing demand for CNN computation necessitates the development of specialized CNN hardware accelerators. In the second part, the talk will be focused on the co-optimization of CNN hardware architecture and dataflow mapping—an intricate problem characterized by an extensive discrete solution space. We will introduce an innovative analytical approach, making a significant advancement over current state-of-the-art methods in improving inference speed and reducing power consumption as well as computational cost.
