演講/活動
2025-07-09 17:22:43陳秋雲【Talk】Physical Design Automation of Transistor Networks
*** You are all welcome to join ***
#Speaker：
Prof. Ricardo Augusto da Luz Reis
Informatics Institute, Federal University of
Rio Grande do Sul
#Time：10:00am~12:00pm, Wednesday, July 16, 2025
#Venue：R108, 1F Engineering Building 4, NYCU
#Expertise：Physical Design Automation, DesignMethodologies, Fault Tolerant Systems,Microelectronics Education
#Abstract：
A way to reduce power consumption is to reduce the number of transistorsused to implement a circuit, as leakage power is proportional to the numberof transistors. It is shown a physical design approach to reduce the number oftransistors needed to perform a task. It is proposed an EDA tool set toautomatically generate the physical design of any transistor network. It showsan important reduction on power, improving also reliability. A standard celllibrary has a limited number of logical functions, and a limited number ofsizing. The talk is target in optimization methods to reduce the number oftransistors of a circuit. The methods allow the realization of any possiblelogical function or transistor network. It is included comparisons withsolutions using the traditional standard cell methodology.
#Speaker：
Prof. Ricardo Augusto da Luz Reis
Informatics Institute, Federal University of
Rio Grande do Sul
#Time：10:00am~12:00pm, Wednesday, July 16, 2025
#Venue：R108, 1F Engineering Building 4, NYCU
#Expertise：Physical Design Automation, DesignMethodologies, Fault Tolerant Systems,Microelectronics Education
#Abstract：
A way to reduce power consumption is to reduce the number of transistorsused to implement a circuit, as leakage power is proportional to the numberof transistors. It is shown a physical design approach to reduce the number oftransistors needed to perform a task. It is proposed an EDA tool set toautomatically generate the physical design of any transistor network. It showsan important reduction on power, improving also reliability. A standard celllibrary has a limited number of logical functions, and a limited number ofsizing. The talk is target in optimization methods to reduce the number oftransistors of a circuit. The methods allow the realization of any possiblelogical function or transistor network. It is included comparisons withsolutions using the traditional standard cell methodology.
